This invention relates to telephone answering devices, and more particularly to a digital telephone answering device having an electronic memory for storing messages therein, and to a technique for testing the message storage memory.
One of the most recent advances in telephone answering device (TAD) technology is the use of random access memory (RAM) instead of magnetic tape for the storage of incoming and outgoing voice messages. Using digital rather than analog means for storing voice messages provides for a more reliable TAD due to more consistent audio quality, elimination of the problems inherent with moving mechanical parts and also elimination of problems caused by malfunction or breakage of the magnetic tape itself. Having messages stored in a RAM chip also allows the user to selectively access a specific message more quickly and easily than if the messages were stored on a cassette tape. Using a conventional analog TAD, the user must wait for the cassette tape to rewind or fast forward in order to hear a specific message, or the user must listen to all of his or her messages again just to replay one particular message.
One drawback to an "all digital" TAD is that the use of RAM is more expensive than the use of magnetic tape. In order to offset the additional cost of using RAM for message storage, it is common to use a less expensive audio random access memory (ARAM) chip in combination with a digital signal processor (DSP) chip. The DSP chip, when used for speech compression and decompression, allows for minimization of RAM use. An ARAM chip, by definition, contains defects, which is the reason for the lower cost. These defects make the chips unacceptable for digital applications in which data storage must be perfect, such as for use in computers, but acceptable for use in applications where a limited number of defects will not affect the quality or efficiency of the audio output. In order for an ARAM to be effective, the chip must be characterized and critical errors or defects mapped prior to use. This insures that information will not be stored in a section of the chip that contains defects that would affect the quality of the audible sound reproduced therefrom.
Many methods exist for testing digital memories and locating defects. All of these methods consume time in proportion to the rigorousness of the test routine and the size of the memory to be tested, which becomes considerable for RAMs of the size used in today's all digital TADs. Thus, the memory must be characterized or tested using a memory test algorithm before any recording can take place, which maps out any faults in the memory.
With digital telephone answering devices available today, the approach is to require an initialization process that takes place as soon as the user powers up the machine, that is, to immediately initiate the memory test algorithm upon power up. This initialization process is necessary for the characterization of the TAD's memory.
However, this results in a "dead time" for the user in which the unit will not respond to key closures or other actions initiated by the user until the characterization or test process is complete, that is, the TAD is non-responsive to all user input. This routine can continue for anywhere from thirty seconds to almost two minutes, as is the case in models such as Panasonic's KX-T2880 and AT&T's 1545. It is common for units to display a countdown timer during this period. Thus, while the memory test algorithm is running, the user faces a non-responsive unit, which can be inconvenient and frustrating for the user.
In order to minimize this effect, manufacturers often compromise the memory characterization or testing process in order to reduce the dead time, possibly resulting in undetected defects in the ARAM and could result in less than desirable performance of the device.
A traditional approach to the dilemma of speeding up memory characterization is to create more efficient test patterns and more efficient means of reading and writing these test patterns. Many times this requires specialized hardware in order to perform the tests. With this approach, there is also a danger of incomplete testing due to time limitations.
U.S. Pat. No. 4,195,770 to Benton et al describes a test generator for detecting functional failures of RAMs, using the traditional approach discussed above. Benton et al tests RAMs by writing patterns into the memory and reading out such patterns again so that they may be compared with the original pattern. Benton et al uses a predetermined number of generated test patterns in accordance with the bit organization of the RAM which is being tested, and continuously compares results during the test sequence to determine if the RAM is functionally good or bad. While this procedure saves time, it does not allow for complete testing of a RAM in a TAD, and does not address the problem of faults that may occur over the life of the RAM.
U.S. Pat. No. 4,066,880 to Salley describes a system for pre-testing all data bit locations and identifying faulty memory sections prior to the entry of any data. Salley recognizes the possibility that a chip which initially is not faulty, can become faulty sometime during its life. Salley continuously monitors the memory for faulty bit locations to overcome this potential problem. While Salley recognizes that the identification of faults in a RAM should take place during normal operation and should not disturb normal operation, Salley does nothing to speed up the testing for initial use.
U.S. Pat. No. 4,715,034 to Jacobson describes a probabilistic method of and system for fast functional testing of RAMs. Functional testing detects faults in the memory that cause it to function incorrectly. Jacobson teaches a method of identifying memory faults using a memory test algorithm that requires as short a testing time as possible while still asserting to be accurate. Jacobson improves efficiency by using a pseudo random method of testing but, as with Benton et al, the increase in testing speed is due to changes in the test pattern. As discussed above, the shorter testing time could result in incomplete testing and, therefore, faults that might prove fatal to the system would go undetected.
Another patent that teaches a method of and system for high-speed, high-accuracy functional testing of memories is U.S. Pat. No. 4,873,705 to Johnson. Johnson teaches an emulator-type test system that is permanently coupled to the bus structure of the unit under test. Johnson also uses a block move and compare method by which data from a range of memory addresses may be accessed, moved and compared. Johnson reduces the time it takes to test one pattern by taking advantage of hardware capabilities of the particular microprocessor that is performing the test. However, Johnson does not test for errors that can occur over time.
U.S. Pat. No. 4,061,908 to de Jonge et al describes yet another example of a method for improving memory testing efficiency by improving the test pattern. This method has the same drawbacks as the methods described above.